1. Technical Field
The present invention relates to a semiconductor memory device, and more particularly to a technique that can be effectively applied to the write operation of a nonvolatile semiconductor memory device, such as a multi-value flash memory having a memory array so configured that each of a plurality of memory cells can store data of a plurality of bits as a threshold voltage in Y access circuits each of a 1×sense latch circuit+2×SRAM configuration.
2. Background Art
According to the findings of research by the present inventor, the following techniques are conceivable for application to a flash memory as an example of nonvolatile semiconductor memory device.
For instance, a flash memory uses nonvolatile memory elements each having a control gate and a floating gate as memory cells, and each memory cell can be configured of one transistor. For such a flash memory, with a view to increasing the storage capacity, the concept of so-called “multi-value” flash memory in which data of two bits are more are stored into each memory cell is proposed. In such a multi-value flash memory, the threshold voltage can be varied stepwise by controlling quantity of electric charges injected into the floating gate, and information of a plurality of bits can be matched with each threshold voltage to store it.
Further for the flash memory referred to above, as the chip size grows with increase in storage capacity, it is required to restrain this growth in chip size. In considering this chip size for instance, since there are many constraints on the area of a memory array consisting of a plurality of memory cells arranged in a grid shape at the intersection points of word lines and bit lines, it is necessary to take note of the square measure of the Y access circuits of this memory array. The Y access circuits of a flash memory may have a circuit configuration, for example, embodying a technique of so-called single end sense formula (see FIG. 4 to be referenced afterwards, for instance).
The Y access circuits using this single end sense formula, as it has a configuration in which the sense latch circuit is arranged at one end of global bit lines, is used for the purpose of reducing the square measure (reducing the number of elements). Further for the Y access circuits, with an eye to reducing the square measure, a technique using a so-called 1×sense latch circuit+2×SRAM configuration is proposed instead of a data transfer circuit having a so-called 1×sense latch circuit+2×data latch circuit configuration. In this 1×sense latch circuit+2×SRAM configuration (see FIG. 6 to be referenced afterwards, for instance), two SRAMs are allocated to a plurality of sense latch circuit in each bank, and data of higher order bits are stored in one of the SRAMs while data of lower order bits are stored in the other.
Incidentally, having studied the aforementioned technique of using the 1×sense latch circuit+2×SRAM configuration for the Y access circuits of the flash memory, the present inventor found the following fact.
The aforementioned 1×sense latch circuit+2×SRAM configuration, unlike the 1×sense latch circuit+2×data latch circuit configuration, involves a problem that it takes time to transfer write data on the SRAMs to the sense latch circuit. For instance, where write data are stored in a data latch circuit, as their transfer from the data latch circuit to the sense latch circuit can be accomplished in parallel, the transfer time required will be only about 1 to 2 μs. By contrast, where write data are stored in a SRAM, as transfer from the SRAM to the sense latch circuit is accomplished serially, each transfer will take about 25 μs.
In view of this problem, the present inventor took note of the write operation of the Y access circuits of the 1×sense latch circuit+2×SRAM configuration and, with an eye to accelerating this write operation, thought of taking into consideration of the number times of data transfer from the SRAM to the sense latch circuit.
An object of the present invention is to provide a nonvolatile semiconductor memory device, such as a multi-value flash memory, capable of realizing acceleration of the this write operation the Y access circuits of the 1×sense latch circuit+2×SRAM configuration.
The above-stated and other objects and novel features of the invention will become more apparent from the following description in the specification when taken in conjunction with the accompanying drawings.